边沿J-K触发器设计实验

实验要求

基于FPGA设计一个边沿J-K触发器集成模块74LS76

image-20211120215604671

实验步骤

image-20211120215639800

具体实验

单个JK触发器模块

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`timescale 1ns / 1ps
module test(J, K, CP, Sd, Rd, Q, FQ);
    input J, K, CP, Sd, Rd;
    output Q, FQ;

    reg Q;

    wire D;
    assign D = J * FQ + ~K * Q;

    always @(negedge CP or negedge Sd or negedge Rd) begin
        if(Sd == 0) Q <= 1'b1;
        else if(Rd == 0) Q <= 1'b0;
        else Q <= D;
    end

    assign FQ = ~Q;
endmodule

74LS76模块

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`timescale 1ns / 1ps
module EdgeJKFF_74LS76(J1, K1, CP1, Sd1, Rd1, Q1, FQ1, 
                       J2, K2, CP2, Sd2, Rd2, Q2, FQ2);
    input J1, K1, CP1, Sd1, Rd1;
    input J2, K2, CP2, Sd2, Rd2;
    output Q1, FQ1;
    output Q2, FQ2;

    // test(J, K, CP, Sd, Rd, Q, FQ);
    test test_1(J1, K1, CP1, Sd1, Rd1, Q1, FQ1);
    test test_2(J2, K2, CP2, Sd2, Rd2, Q2, FQ2);
endmodule

板极验证

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set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN V5} [get_ports J1]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN T4} [get_ports K1]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Sd1]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN V6} [get_ports Sd1]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Rd1]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN T5} [get_ports Rd1]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CP1]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN N17} [get_ports CP1]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN U6} [get_ports Q1]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN R5} [get_ports FQ1]

set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN T14} [get_ports J2]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN V15} [get_ports K2]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Sd2]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN R15} [get_ports Sd2]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Rd2]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN U16} [get_ports Rd2]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CP2]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN U17} [get_ports CP2]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN T16} [get_ports Q2]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN V17} [get_ports FQ2]